The present invention relates to semiconductor devices, and more specifically, to three-dimensional (3D) semiconductor devices.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary metal-oxide-semiconductor field-effect transistor, which are typically referred to as CMOS devices, have become widely used in the semiconductor industry. These CMOS devices include both n-type and p-type (NMOS and PMOS) transistors, that promote the fabrication of logic and various other integrated circuitry.
The escalating demands for high density and performance associated with ultra large scale integrated (ULSI) circuit devices have let to certain design features, such as shrinking gate lengths, high reliability and increased manufacturing throughput. The continued reduction of design features has challenged the limitations of conventional fabrication techniques. Three-dimensional semiconductor devices, such as fin-type semiconductor devices (referred to as finFETs), typically include dielectric gate spacers formed on sidewalls of the gate stack to isolate the gate stack from the adjacent source/drain (S/D) regions.
The continued demand to scale down the size of finFET devices has resulted in forming semiconductor fins with reduced fin pitches.